In a MOSFET structure, it is desirable to have a channel as narrow as possible to enhance control over the channel by the gate, so as to suppress the short channel effects. However, when the channel thickness is smaller than 10 nm, device performance may be severely influenced due to reduction of carrier mobility with the decrease of the channel thickness. Particularly, the channel near the source end may be much more influenced. While at the drain end, the channel thickness plays a minor role on the carrier mobility because of high field saturation.
Drain Induction Barrier Lower (DIBL) is an undesirable effect in a short channel device. when the channel length decreases, the source-drain voltage increases such that the depletion regions in PN junctions of source/drain regions become closer. As a result, the electric line in the channel may traverse from the drain region to the source region and the barrier height at the source decreases, so that number of the carrier from the source to the channel increases and the current at the drain end increases. With further decrease of the channel length, DIBL has a much severe impact such that the threshold voltage of the transistor decreases, voltage gain of the device is reduced, and integration level of Very Large Scale Integtated Circuit is restricted.
It has been an urgent challenge to be solved for providing a method for manufacturing a MOS transistor with effectively reduced DIBL current.